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Verilog / VHDL - little vs big Endian

by: Robin Tsang
|
May 10, 2002

Version: 0.0001

Type: Full Script

Category: Algorithms

License: GNU General Public License

Description: A script for you to easily to change all big-endian wires to big-endian in a Verilog file. this script was written for an x86 machine where there are only 8, 16, 32 bit registers. if you have a machine for 64 bits, modiy the code to what you need. the variable i used in the script is called ir_in[127:96] the file this script reads must be called file.v have fun. it'll save you some time.



<?
$lines = file("file.v");

$search = array("/ir_in\[(\d{1,3}):(\d{1,3})\]/e");
$replace = array("fix($1, $2)");

function fix($hi, $lo){

	switch($hi-$lo)
	{
	  case 7:
		return "ir_in[".$hi.":".$lo."]";
	  break;
	  case 15:
		return "{ir_in[".($lo+7).":".$lo."], ir_in[".($lo+15).":".($lo+8)."]}";
	  break;
	  case 31:
		return "{ir_in[".($lo+7).":".$lo."], ir_in[".($lo+15).":".($lo+8)."], ir_in[".($lo+23).":".($lo+16)."], ir_in[".($lo+31).":".($lo+24)."]}";
	  break;
	  default:
		echo "HELP! hi-lo=".($hi-$lo)."\n";
	  break;
	}

	return "HELP! hi-lo=".($hi-$lo);
}

for($i=0;$i<count($lines);$i++)
{
	echo preg_replace($search, $replace, $lines[$i]);
}

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